High Performance ATE & DUT Boards

Liberty Research was founded by engineers with test and applications background in the Semiconductor industry at foundries and IDMs. Liberty Research offers comprehensive Test Cell Solutions for the Semiconductor Test Engineering and Product Development markets.

Our engineers have a long history of bringing complete solutions – from definition and design all the way through assembly and test.

Liberty uses a Flexible Staff approach to the resource alignment for the design of ATE boards. We have alliances with Board Designers in Singapore, Shanghai, San Jose and Phoenix.

All of the board management is guided by a project engineer from the Cupertino office and the workload is distributed to where it can be done to the specifications and timing that is needed.

When the boards require High Speed Design, the boards will be designed in Cadence Allegro or Mentor Pads software to insure the accuracy and to allow for interface to Signal Integrity software.

Technical Advantages

High Speed Design Experience
Mixed signal board designs
RF experience
State of the Art Software Tools from Cadence and Mentor
LVS layout vs schematic
1 contact person for design
Schematic Generation – Orcad
Simulation: What if analysis of dielectrics, critical dimensions, vias
Development of Design Rules

Capabilities

Material Selection: FR-4, 408, Getek, Rogers, Taconic
Minimum: 3 mil traces and spaces
Multi-layer up to 36 layers
Via Aspect ratio of 30:1 and higher
HDI and blind and buried vias
To 36” x 28” out board dimensions
Co-axial pogo ring interfaces

Testers

Agilent-Teradyne–LTX
Credence